Subject: devel-digest V2 #166
From: [email-masked] (devel-digest)
To: [email-masked]

devel-digest           Tuesday, May 11 1999           Volume 02 : Number 166

In this issue:

    Re: "missing memory"
    Enabling the Flash Write signal
    Re: "missing memory"
    Re: Enabling the Flash Write signal
    Re: Enabling the Flash Write signal

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Date: Mon, 10 May 1999 17:58:39 +0000
From: Ralph Siemsen <[email-masked]>
Subject: Re: "missing memory"

"Eric A. Perlman" wrote:
> 
> The new nettrom works perfectly, thanks!

Great... have you tried any esoteric booting options (tftp, nfs, etc?)

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------------------------------

Date: Mon, 10 May 1999 11:10:10 -0700
From: Greg Miller <[email-masked]>
Subject: Enabling the Flash Write signal

This is a bit of an offbeat question, but . . . 

I've my own JTAG Suite that I intend to make public sometime in the near
future.  For systems that contain a form of embedded debugging, I
provide a certain degree of support (for instance, for ARM *DI* systems,
I provide transactions, breakpoints, single-stepping, etc.; I'm currently
licensing similar specs for the PPC systems from IBM (well, IBM's PPCs;
Motorola has taken a different direction on the PowerPC 5xx's).  I also
provide boundary-scan support from .bsdl files for systems that support
only that.

Among my chores in tesitng and playing with this was to write some code
to be able to reflash the Netwinder's Flash ROM via the JTAG ports. [albeit slowly]
I first approached it via the SA-110, but had no end of trouble.  
Using the 21285's JTAG port, however, I've managed to issue both read
and write cycles against the ROM.  

With one problem.

The Netwinder appears to have put an 'and' gate between A31 (nWE for
ROM accesses) from the 21285 and the Flash ROM part itself.  The original
'switch' for enabling this appears to be accessable via the '553.

Dealing with this isn't a big deal, except that it's hanging off of the
PCI bus.  PCI isn't anywhere near as time-convenient to deal with via
JTAG as single ROM transactions.  [Ie, certain things happen at X clocks
after other events; that kind of accuracy is impossible for a slow interface
like JTAG unless the JTAG is also controlling the bus clock.]

Thus, I'm asking the folks at HCC that originally did their
JTAG-programming tool if they'd be willing to save me a LOT of time
and let me know what the minimum setups they had to do to get the bits
set in the shift-register-logic hanging off of the '553.  I can eventually
sort things out, but if anyone's feeling charitable, I'd appreciate 
any time-savings you might be willing to grant me.  :')

Thanks!

 - Greg Miller

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------------------------------

Date: Mon, 10 May 1999 14:05:40 -0400 (EDT)
From: [email-masked]
Subject: Re: "missing memory"

On Mon, 10 May 1999, Ralph Siemsen wrote:

> "Eric A. Perlman" wrote:
> > 
> > The new nettrom works perfectly, thanks!
> 
> Great... have you tried any esoteric booting options (tftp, nfs, etc?)

I've successfully used tftp with the root file system on nfs to install
the titan distribution on my netwinder using the 2.0.8c nettrom.

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------------------------------

Date: Mon, 10 May 1999 16:36:38 -0400
From: Woody Suwalski <[email-masked]>
Subject: Re: Enabling the Flash Write signal

If I understand correctly, U want to JTag the Netwinder flash while the
Footbridge and CPU are in "JTag mode". If so - U do not need to fiddle with
the PCI side of flash write enable gate - simply pull down pin 4 on the JTag
programming socket (14 pin DIP close to the orange button) or pin 4 on the
edge connector in the back (under the fan)...

Needles to say, that while we are happy to support U, if U destroy your
machine - U are on your own... ;-(

Woody

Greg Miller wrote:
> 
> This is a bit of an offbeat question, but . . .
> 
> I've my own JTAG Suite that I intend to make public sometime in the near
> future.  For systems that contain a form of embedded debugging, I
> provide a certain degree of support (for instance, for ARM *DI* systems,
> I provide transactions, breakpoints, single-stepping, etc.; I'm currently
> licensing similar specs for the PPC systems from IBM (well, IBM's PPCs;
> Motorola has taken a different direction on the PowerPC 5xx's).  I also
> provide boundary-scan support from .bsdl files for systems that support
> only that.
> 
> Among my chores in tesitng and playing with this was to write some code
> to be able to reflash the Netwinder's Flash ROM via the JTAG ports. [albeit slowly]
> I first approached it via the SA-110, but had no end of trouble.
> Using the 21285's JTAG port, however, I've managed to issue both read
> and write cycles against the ROM.
> 
> With one problem.
> 
> The Netwinder appears to have put an 'and' gate between A31 (nWE for
> ROM accesses) from the 21285 and the Flash ROM part itself.  The original
> 'switch' for enabling this appears to be accessable via the '553.
> 
> Dealing with this isn't a big deal, except that it's hanging off of the
> PCI bus.  PCI isn't anywhere near as time-convenient to deal with via
> JTAG as single ROM transactions.  [Ie, certain things happen at X clocks
> after other events; that kind of accuracy is impossible for a slow interface
> like JTAG unless the JTAG is also controlling the bus clock.]
> 
> Thus, I'm asking the folks at HCC that originally did their
> JTAG-programming tool if they'd be willing to save me a LOT of time
> and let me know what the minimum setups they had to do to get the bits
> set in the shift-register-logic hanging off of the '553.  I can eventually
> sort things out, but if anyone's feeling charitable, I'd appreciate
> any time-savings you might be willing to grant me.  :')
> 
> Thanks!
> 
>  - Greg Miller
>
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------------------------------

Date: Mon, 10 May 1999 12:50:32 -0700 (PDT)
From: Greg Miller <[email-masked]>
Subject: Re: Enabling the Flash Write signal

On 10-May-99 Woody Suwalski wrote:
> If I understand correctly, U want to JTag the Netwinder flash while the
> Footbridge and CPU are in "JTag mode". If so - U do not need to fiddle with
> the PCI side of flash write enable gate - simply pull down pin 4 on the JTag
> programming socket (14 pin DIP close to the orange button) or pin 4 on the
> edge connector in the back (under the fan)...

Aha!  So *that* is what '/JTAG_CE' is for.  When either one of the hardware
people or Pat (or someone?) posted the pinouts of the JTAG connectors to me
many months ago, they listed pin 4 as such, but nobody seemed to remember
what it was for.  

> Needless to say, that while we are happy to support U, if U destroy your
> machine - U are on your own... ;-(
> 
> Woody

Sure.  However, the only reason I ever bought the thing was to play
with the StrongARM/PCI bus, not as a (gasp!) Linux box, so trashing of
hardware is an acceptable risk for me.  [I've obviously already voided
the hell out of the warranty.]

Thanks a bunch, Woody!  I'll make a small wiring change tonight and
then check my analyzer to see if /WE is getting asserted w/ A31. 

 - Greg

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